http://dl.gi.de/handle/20.500.12116/29355 2026-07-21T13:37:57Z 2026-07-21T13:37:57Z Kochs, Hans-Dieter Petersen, Jörg http://dl.gi.de/handle/20.500.12116/29400 2019-10-30T11:53:49Z 2004-01-01T00:00:00Z

A framework for dependability evaluation of mechatronic units Kochs, Hans-Dieter; Petersen, Jörg Brinkschulte, Uwe; Becker, Jürgen; Fey, Dietmar; Großpietsch, Karl-Erwin; Hochberger, Christian; Maehle, Erik; Runkler, Thomas A. Mechatronic units are characterized by a complex interaction of functions from mechanics, electronics, communication and computer systems. These different fields of technology as well as influences from the operating environment must be reflected in the dependability consideration, for which so far no comprehensive framework exists. In this contribution, a framework for consideration of dependability of mechatronic units starting from a definition of the term 'dependability of mechatronic units' is proposed. Special attention is put on to the influence factors including human-machine interfaces, and real-world constraints, which thoroughly have to be identified and considered. Following questions have to be regarded: What is understood by the term dependability of mechatronic units? Which influencing factors have to be considered? How the dependability is assessed? This contribution also wants to initiate a scientific discussion outside the fault tolerance community.

2004-01-01T00:00:00Z Morozov, A. Saposhnikov, V. V. Saposhnikow, Vl. V. Gössel, M. http://dl.gi.de/handle/20.500.12116/29398 2019-10-30T11:53:48Z 2004-01-01T00:00:00Z

Complementary circuits for on-line detection for 1-out-of-3 codes Morozov, A.; Saposhnikov, V. V.; Saposhnikow, Vl. V.; Gössel, M. Brinkschulte, Uwe; Becker, Jürgen; Fey, Dietmar; Großpietsch, Karl-Erwin; Hochberger, Christian; Maehle, Erik; Runkler, Thomas A. In this paper a new method for concurrent checking of an arbitrarily given combinational multi-output circuit f by use of an 1-out-of-3 code is presented. The circuit f is completed by an additional multi-output circuit g in such a way that the XOR-sums of the corresponding outputs of f or of the inverted outputs of f and g are elements of a 1-out-of-3 code. For efficiently checking the 1-out-of-3 encoded outputs also a new self-checking checker based on a three-rail checker cell is proposed. Index Terms: 1-out-of-3 code, on-line error detection, complementary circuit, totally self-checking 1-out-of-3 code checker.

2004-01-01T00:00:00Z Trikaliotis, Spiro http://dl.gi.de/handle/20.500.12116/29397 2019-10-30T11:53:48Z 2004-01-01T00:00:00Z

Utilizing fault tolerance for achieving QoS in Ad-hoc networks Trikaliotis, Spiro Brinkschulte, Uwe; Becker, Jürgen; Fey, Dietmar; Großpietsch, Karl-Erwin; Hochberger, Christian; Maehle, Erik; Runkler, Thomas A. Ad-hoc networks consist of many independent wireless nodes which communicate without the help of an infrastructure. Since this type of networks exhibits a dynamic topology, that is, the nodes move very frequently, it is hard to establish some quality-of-service (QoS) in this scenario. This paper presents an approach which accomplishes this. QoS is guaranteed in the sense that the network either can offer these parameters, or it informs the source that it cannot do this anymore. While this guarantee is not so stringent that the network really can guarantee it in every case, in most cases, a QoS degradation as well as a link break will be announced to the sender beforehand, allowing it and the application to take some counter-measures such as putting the system in a safe state before the QoS degrades.

2004-01-01T00:00:00Z Sogomonyan, E. S. Marienfeld, D. Ocheretnij, V. Gössel, M. http://dl.gi.de/handle/20.500.12116/29399 2019-10-30T11:53:48Z 2004-01-01T00:00:00Z

Self-checking carry-select adder with sum-bit duplication Sogomonyan, E. S.; Marienfeld, D.; Ocheretnij, V.; Gössel, M. Brinkschulte, Uwe; Becker, Jürgen; Fey, Dietmar; Großpietsch, Karl-Erwin; Hochberger, Christian; Maehle, Erik; Runkler, Thomas A. In this paper the first code-disjoint totally self-checking carry-select adder is proposed. The adder blocks are fast ripple adders with a single NAND-gate delay for carry-propagation per cell. In every adder block both the sum-bits and the corresponding inverted sum-bits are simultaneously implemented. The parity of the input operands is checked against the X OR-sum of the propagate signals. For 64 bits area and maximal delay are determined by the SYNOPSYS CAD tool of the EUROCHIP project. Compared to a 64 bit carry-select adder without error detection the delay of the most significant sum-bit does not increase. Compared to a completely duplicated code-disjoint carry-select adder we save 240 X OR-gates.

2004-01-01T00:00:00Z