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<title>PARS-Mitteilungen 2017</title>
<link>http://dl.gi.de/handle/20.500.12116/31834</link>
<description/>
<pubDate>Wed, 22 Jul 2026 22:10:46 GMT</pubDate>
<dc:date>2026-07-22T22:10:46Z</dc:date>
<item>
<title>An Image Processing Operator Language for Design and Synthesis of Smart Camera Architectures</title>
<link>http://dl.gi.de/handle/20.500.12116/31946</link>
<description>An Image Processing Operator Language for Design and Synthesis of Smart Camera Architectures
Hartmann, Christian; Häublein, Konrad; Pfundt, Benjamin; Reichenbach, Marc; Fey, Dietmar
Recent trends showed a rise of heterogeneous hardware architectures for image processing applications. Due to the usage of these camera systems in the embedded field, the reduction of area and power consumption became essential. Standard CPUs are not suitable in the embedded field, because of their lavish commerce regarding power and area consumption. Embedded applications have strict constraints regarding these parameters. Therefore, optimized and specialized hardware is required resulting in a heterogeneous system architecture. Designing such a system is a challenging and error-prone task. In the design process, software and hardware skills are needed. Programming skills in different programming and design languages are necessary. For reducing the complexity a common language which can easily be mapped on different hardware architectures combined with a synthesis framework is needed. With the Image Processing Operator Language (IPOL) the description of heterogeneous systems with one language become possible. The synthesis framework called Image Processing Architecture Synthesis (IPAS) completes the domain-specific language (DSL) as an underlying mapping methodology.
</description>
<pubDate>Sun, 01 Jan 2017 00:00:00 GMT</pubDate>
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<dc:date>2017-01-01T00:00:00Z</dc:date>
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<item>
<title>Predicting Efficient Execution with Source Code Analysis in a Heterogeneous Environment</title>
<link>http://dl.gi.de/handle/20.500.12116/31944</link>
<description>Predicting Efficient Execution with Source Code Analysis in a Heterogeneous Environment
Hellwig, Markus; Becker, Thomas
Finding a good schedule for the tasks of an application is a critical step for the efficient usage of heterogeneous systems. A good schedule can only be found with information about the tasks to be scheduled. In a dynamic system, this information is normally only available after each task is at least executed once, thereby creating an initial overhead until a good schedule can be created. Therefore, we introduce a method based on static code analysis and machine learning algorithms to predict the fastest processor of a given OpenCL task before runtime by classification which helps to reduce this initial overhead. We show how we used a static code analysis implementation based on Clang to generate training data on a set of 10 different heterogeneous processors including Intel, AMD and Nvidia GPUs, a Intel Xeon Phi and Intel CPUs. This training data was used to generate prediction models via several different machine learning algorithms including Random Forest and k-Nearest Neighbour and then evaluate the models by predicting the fastest processor out of two and more processors via classification.
</description>
<pubDate>Sun, 01 Jan 2017 00:00:00 GMT</pubDate>
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<dc:date>2017-01-01T00:00:00Z</dc:date>
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<item>
<title>Tracing of Multi-Threaded Java Applications in Score-P Using JVMTI and User Instrumentation</title>
<link>http://dl.gi.de/handle/20.500.12116/31945</link>
<description>Tracing of Multi-Threaded Java Applications in Score-P Using JVMTI and User Instrumentation
Frenzel, Jan; Feldhoff, Kim; Jäkel, René; Müller-Pfefferkorn, Ralph
Over the past years, parallel Java applications received a substantial boost in the research field of High Performance Computing, especially in the field of Big Data Analytics by the development of Java-based frameworks, i. e., Apache Hadoop, Flink or Spark, amongst others, for processing large-scale datasets. Analyzing the performance of said Big Data frameworks in particular, and multi-threaded Java applications in general, is indispensable for efficient execution. Due to the high number of threads, this requires a scalable runtime performance measurement infrastructure. The established, open-source tracing framework Score-P provides such an infrastructure, but did not support (parallel) Java applications, previously. We added support for tracing multi-threaded Java applications to Score-P by implementing two instrumentation approaches. The first instrumentation approach is based on the Java Virtual Machine tool interface (JVMTI) and allows to easily trace an application without source code modifications. The second instrumentation approach allows to manually modify sources via API functions such that only those parts of an application are recorded which the user is interested in. Both instrumentation approaches were successfully applied to the LU kernel of the established Java benchmark suite SPECjvm2008 at a modern HPC machine. We show the quality of the implementations by determining the tracing overheads of the instrumented versions for different test scenarios using varying numbers of Java threads, and thus, varying numbers of recorded events.
</description>
<pubDate>Sun, 01 Jan 2017 00:00:00 GMT</pubDate>
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<dc:date>2017-01-01T00:00:00Z</dc:date>
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<item>
<title>A Distributed Hash Table using One-sided Communication in MPI</title>
<link>http://dl.gi.de/handle/20.500.12116/31943</link>
<description>A Distributed Hash Table using One-sided Communication in MPI
Sobe, Peter; Graupner, Tom; Hennig, Florian
The Message Passing Interface (MPI) can be applied to implement data structures that are distributed across process memory, such as distributed arrays or hash tables. In this paper a hash table implementation
is described that employs one-sided communication in case of collision-free access. Collisions of data entries within the hash table are treated using dynamic overflow memory and two-sided communication. This leads to a two-level communication architecture that combines one-sided and two-sided operations in a data structure and the related access operations. This approach circumvents the problem of dynamic and unforeseen size and arrangement of data structures in shared memory that would be hard to manage using solely one-sided communication.
</description>
<pubDate>Sun, 01 Jan 2017 00:00:00 GMT</pubDate>
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<dc:date>2017-01-01T00:00:00Z</dc:date>
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