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<title>it - Information Technology 62(5-6) - August 2020</title>
<link>http://dl.gi.de/handle/20.500.12116/36572</link>
<description/>
<pubDate>Wed, 22 Jul 2026 22:10:54 GMT</pubDate>
<dc:date>2026-07-22T22:10:54Z</dc:date>
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<title>From transistor level to cyber physical/hybrid systems: Formal verification using automatic compositional abstraction</title>
<link>http://dl.gi.de/handle/20.500.12116/36580</link>
<description>From transistor level to cyber physical/hybrid systems: Formal verification using automatic compositional abstraction
Tarraf, Ahmad; Hedrich, Lars
In this paper we present a methodology to automatically generate an accurate behavioral model from an analog circuit description. The current machine learning method is limited to circuits with up to 80 transistors, limiting our approach to small and mid size circuit blocks due to a state explosion problem. However, if complex building blocks such as IOT systems should be modeled, the current approach needs to recoup with feasible simulation and modeling time. To come up with a solution for this problem, we extend the current method by a compositional approach. The approach is illustrated upon an example from the area of autonomous driving. Our method decomposes this large example into smaller building blocks and models each of them automatically. All models are combined into a compositional hybrid automaton of the whole complex system. Compared to the original state space, the building blocks operate on smaller and reduced state spaces and hence drastically reduce the complexity. Using a back-transformation on the compositional automaton, all values from the original state space can be reconstructed. Moreover, we perform a formal verification on the generated compositional automaton. Results from a meaningful example are presented and discussed.
</description>
<pubDate>Wed, 01 Jan 2020 00:00:00 GMT</pubDate>
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<dc:date>2020-01-01T00:00:00Z</dc:date>
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<title>Exploring hardware accelerator offload for the Internet of Things</title>
<link>http://dl.gi.de/handle/20.500.12116/36576</link>
<description>Exploring hardware accelerator offload for the Internet of Things
Cooke, Ryan A.; Fahmy, Suhaib A.
The Internet of Things is manifested through a large number of low-capability connected devices. This means that for many applications, computation must be offloaded to more capable platforms. While this has typically been cloud datacenters accessed over the Internet, this is not feasible for latency sensitive applications. In this paper we investigate the interplay between three factors that contribute to overall application latency when offloading computations in IoT applications. First, different platforms can reduce computation latency by differing amounts. Second, these platforms can be traditional server-based or emerging network-attached, which exhibit differing data ingestion latencies. Finally, where these platforms are deployed in the network has a significant impact on the network traversal latency. All these factors contributed to overall application latency, and hence the efficacy of computational offload. We show that network-attached acceleration scales better to further network locations and smaller base computation times that traditional server based approaches.
</description>
<pubDate>Wed, 01 Jan 2020 00:00:00 GMT</pubDate>
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<dc:date>2020-01-01T00:00:00Z</dc:date>
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<title>Internet of Things</title>
<link>http://dl.gi.de/handle/20.500.12116/36575</link>
<description>Internet of Things
Steinhorst, Sebastian
Article Internet of Things was published on December 1, 2020 in the journal it - Information Technology (volume 62, issue 5-6).
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<pubDate>Wed, 01 Jan 2020 00:00:00 GMT</pubDate>
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<dc:date>2020-01-01T00:00:00Z</dc:date>
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<title>Modeling advanced security aspects of key exchange and secure channel protocols</title>
<link>http://dl.gi.de/handle/20.500.12116/36574</link>
<description>Modeling advanced security aspects of key exchange and secure channel protocols
Günther, Felix
Secure connections are at the heart of today’s Internet infrastructure, protecting the confidentiality, authenticity, and integrity of communication. Achieving these security goals is the responsibility of cryptographic schemes, more specifically two main building blocks of secure connections. First, a key exchange protocol is run to establish a shared secret key between two parties over a, potentially, insecure connection. Then, a secure channel protocol uses that shared key to securely transport the actual data to be exchanged. While security notions for classical designs of these components are well-established, recently developed and standardized major Internet security protocols like Google’s QUIC protocol and the Transport Layer Security (TLS) protocol version 1.3 introduce novel features for which supporting security theory is lacking. In my dissertation [20], which this article summarizes, I studied these novel and advanced design aspects, introducing enhanced security models and analyzing the security of deployed protocols. For key exchange protocols, my thesis introduces a new model for multi-stage key exchange to capture that recent designs for secure connections establish several cryptographic keys for various purposes and with differing levels of security. It further introduces a formalism for key confirmation, reflecting a long-established practical design criteria which however was lacking a comprehensive formal treatment so far. For secure channels, my thesis captures the cryptographic subtleties of streaming data transmission through a revised security model and approaches novel concepts to frequently update key material for enhanced security through a multi-key channel notion. These models are then applied to study (and confirm) the security of the QUIC and TLS 1.3 protocol designs.
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<pubDate>Wed, 01 Jan 2020 00:00:00 GMT</pubDate>
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<dc:date>2020-01-01T00:00:00Z</dc:date>
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