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<title>it - Information Technology 61(1) - Februar 2019</title>
<link>http://dl.gi.de/handle/20.500.12116/36632</link>
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<pubDate>Thu, 23 Jul 2026 19:11:29 GMT</pubDate>
<dc:date>2026-07-23T19:11:29Z</dc:date>
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<title>Security validation of VP-based SoCs using dynamic information flow tracking</title>
<link>http://dl.gi.de/handle/20.500.12116/36638</link>
<description>Security validation of VP-based SoCs using dynamic information flow tracking
Goli, Mehran; Hassan, Muhammad; Große, Daniel; Drechsler, Rolf
Modern System-on-Chips (SoCs) are notoriously insecure. Hence, the fundamental security feature of IP isolation is heavily used, e. g., secured Memory Mapped IOs (MMIOs), or secured address ranges in case of memories, are marked as non-accessible. One way to provide strong assurance of security is to define isolation as information flow policy in hardware using the notion of non-interference. Since, an insecure hardware opens up the door for attacks across the entire system stack (from software down to hardware), the security validation process should start as early as possible in the SoC design cycle, i. e. at Electronic System Level (ESL). Hence, in this paper we propose the first dynamic information flow analysis at ESL. Our approach allows to validate the run-time behavior of a given SoC implemented using Virtual Prototypes (VPs) against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity). Experiments show the applicability and efficacy of the proposed method on various VPs including a real-world system.
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<pubDate>Tue, 01 Jan 2019 00:00:00 GMT</pubDate>
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<dc:date>2019-01-01T00:00:00Z</dc:date>
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<title>Evaluation of (power) side-channels in cryptographic implementations</title>
<link>http://dl.gi.de/handle/20.500.12116/36636</link>
<description>Evaluation of (power) side-channels in cryptographic implementations
Bache, Florian; Plump, Christina; Wloka, Jonas; Güneysu, Tim; Drechsler, Rolf
Side-channel attacks enable powerful adversarial strategies against cryptographic devices and encounter an ever-growing attack surface in today’s world of digitalization and the internet of things. While the employment of provably secure side-channel countermeasures like masking have become increasingly popular in recent years, great care must be taken when implementing these in actual devices. The reasons for this are two-fold: The models on which these countermeasures rely do not fully capture the physical reality and compliance with the requirements of the countermeasures is non-trivial in complex implementations. Therefore, it is imperative to validate the SCA-security of concrete instantiations of cryptographic devices using measurements on the actual device. In this article we propose a side-channel evaluation framework that combines an efficient data acquisition process with state-of-the-art confidence interval based leakage assessment. Our approach allows a sound assessment of the potential susceptibility of cryptographic implementations to side-channel attacks and is robust against noise in the evaluation system. We illustrate the steps in the evaluation process by applying them to a protected implementation of AES.
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<pubDate>Tue, 01 Jan 2019 00:00:00 GMT</pubDate>
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<dc:date>2019-01-01T00:00:00Z</dc:date>
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<title>Modern random number generator design – Case study on a secured PLL-based TRNG</title>
<link>http://dl.gi.de/handle/20.500.12116/36635</link>
<description>Modern random number generator design – Case study on a secured PLL-based TRNG
Fischer, Viktor; Bernard, Florent; Bochard, Nathalie
Random number generators (RNGs) are basic cryptographic primitives. They are used to generate cryptographic keys, initialization vectors, challenges and nonces in cryptographic protocols, and random masks in countermeasures against side channel attacks. RNGs designed for cryptography must generate unpredictable random numbers. According to recent security standards, the unpredictability of generated random numbers must be thoroughly evaluated. In this paper, we provide a concrete example – a phase-locked loop based RNG protected by novel dedicated embedded tests, on which we show how stringent security requirements including unpredictability of generated numbers can be met, while respecting the standards.
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<pubDate>Tue, 01 Jan 2019 00:00:00 GMT</pubDate>
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<dc:date>2019-01-01T00:00:00Z</dc:date>
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<title>Hardware-oriented security</title>
<link>http://dl.gi.de/handle/20.500.12116/36634</link>
<description>Hardware-oriented security
Polian, Ilia
Article Hardware-oriented security was published on February 1, 2019 in the journal it - Information Technology (volume 61, issue 1).
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<pubDate>Tue, 01 Jan 2019 00:00:00 GMT</pubDate>
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<dc:date>2019-01-01T00:00:00Z</dc:date>
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