Detection and correction of logic errors using extra time slots

Abstract

Digital integrated circuits fabricated in nano-technologies have first shown to be more vulnerable to transient errors effects than their predecessors. But they also show effects of stressinduced defects resulting in early life-time failures. In general, power dissipation problems and dielectric stress, due to high field strength, are the main reasons for shortened life-time expectations. On the other hand, system designers require highly reliable and long-time dependable hardware, for example in automotive applications. On-line error detection andcompensation using either codes or, in the more general case, double or triple modular redundancy (DM R and TM R), has been used for decades, but causes higher power dissipation in nano-logic, additional stress, and is therefore no cure in terms of life-time extension. Savings on hardware and power are possible, if resources can be re-allocated to produce local TM R upon demand. However, such techniques may cause sudden signal delays after the detection of errors, which are not easy to handle in synchronous systems. In this paper we present a pseudo-TM R approach, which has little influence on timing in the “good case” and performs a regular error correction within 3 extra clock cycles under error correction without limits on the fault model .