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dc.contributor.authorKeller, Jörg
dc.contributor.authorKessler, Christoph
dc.contributor.authorKönig, Kalle
dc.contributor.authorHeenes, Wolfgang
dc.contributor.editorNagel, Wolfgang E.
dc.contributor.editorHoffmann, Rolf
dc.contributor.editorKoch, Andreas
dc.date.accessioned2019-05-06T10:35:46Z
dc.date.available2019-05-06T10:35:46Z
dc.date.issued2008
dc.identifier.isbn978-3-88579-218-5
dc.identifier.issn1617-5468
dc.identifier.urihttp://dl.gi.de/handle/20.500.12116/22269
dc.description.abstractSorting large data sets has always been an important application, and hence has been one of the benchmark applications on new parallel architectures. We present a parallel sorting algorithm for the Cell processor that combines elements of bitonic sort and merge sort, and reduces the bandwidth to main memory by pipelining. We present runtime results of a partial prototype implementation and simulation results for the complete sorting algorithm, that promise performance advantages over previ- ous implementations.en
dc.language.isoen
dc.publisherGesellschaft für Informatik e. V.
dc.relation.ispartof9th workshop on parallel systems and algorithms – workshop of the GI/ITG special interest groups PARS and PARVA
dc.relation.ispartofseriesLecture Notes in Informatics (LNI) - Proceedings, Volume P-124
dc.subjectParallel Sort
dc.subjectMerge Sort
dc.subjectCell Processor
dc.subjectHybrid Sort
dc.titleHybrid Parallel Sort on the Cell Processoren
dc.typeText/Conference Paper
dc.pubPlaceBonn
mci.reference.pages107-112
mci.conference.sessiontitleRegular Research Papers
mci.conference.locationDresden
mci.conference.dateFebruary 26th, 2008


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