Optimization potential of CMOS power by wire spacing

dc.contributor.author	Zuber, Paul
dc.contributor.author	Müller, Florian Helmut
dc.contributor.author	Stechele, Walter
dc.contributor.editor	Cremers, Armin B.
dc.contributor.editor	Manthey, Rainer
dc.contributor.editor	Martini, Peter
dc.contributor.editor	Steinhage, Volker
dc.date.accessioned	2019-10-11T07:41:21Z
dc.date.available	2019-10-11T07:41:21Z
dc.date.issued	2005
dc.identifier.isbn	3-88579-396-2
dc.identifier.issn	1617-5468
dc.identifier.uri	http://dl.gi.de/handle/20.500.12116/28057
dc.description.abstract	In this work, we identify the power-optimal wire spacing as a geometric program. Its solution is a vector of individual distances between the wires. To quantify the optimization potential by this method we model the output of a grid based router with a set of parallel wires. A comparison of the power values before and after geometric optimization shows that the optimization potential lies well in the two digit percent zone for a representative circuit model in a 130nm process.	en
dc.language.iso	en
dc.publisher	Gesellschaft für Informatik e.V.
dc.relation.ispartof	Informatk 2005. Informatik Live! Band 1
dc.relation.ispartofseries	Lecture Notes in Informatics (LNI) - Proceedings, Volume P-67
dc.title	Optimization potential of CMOS power by wire spacing	en
dc.type	Text/Conference Paper
dc.pubPlace	Bonn
mci.reference.pages	344-348
mci.conference.sessiontitle	Regular Research Papers
mci.conference.location	Bonn
mci.conference.date	19.-22. September 2005