Generation of distributed arithmetic designs for reconfigurable applications

Abstract

We present a tool for design and implementation of reconfigurable computing applications based on the use of distributed arithmetic. Our tool provides the user the possibility to investigate different tradeoffs like area vs speed for his design. After simulation of the design, a synthesizable HDL code for a reconfigurable platform can be generated. Beside the existing fixed-point solutions for real numbers, we present a new approach to handle real numbers in the IEEE 754 floating-point format. The tool is used in the implementation of two applications. The first one is the implementation of a recursive convolution algorithm for time domain simulation of multimode intrasystem interconnects and the second one is the implementation of adaptive mechatronical multi-controller systems.