Parallelism in a CRC coprocessor

Abstract

Cyclic Redundancy Checks (CRC) constitute an important class of hash functions for detecting changes in data blocks after transmission, storage and retrieval, or distributed processing. Currently, most sequential methods based on Horner's scheme are applied with some extensions or modifications. The flexibility of these methods with respect to the generator polynomial and the sequence of data processing is limited. A newly proposed algorithm and architecture [DW03, DW04] offer a high degree of flexibility in several aspects and provide high performance with a modest investment in hardware. The algorithm has inherent freedom for parallel processing on several levels, which is exploited in the proposed architecture. An early implementation gives quantitative results on cost and performance and suggests possible extensions and improvements. The algorithm, a typical system architecture, and the coprocessor's structure are described in this paper with an emphasis on parallelism.