Static Analysis Methodologies for WCET Calculating with Asynchronous IO

Abstract

The estimation of the upper bound of the WCET is one of the hardest challenges in the analysis of safety critical real time applications. Since a long time, the static WCET estimation of single core CPU-focused systems without shared resources has been investigated and can now be regarded as solved. The WCET analysis with shared resources is not feasible with current practice due to the lack of information about the internal timing, especially the IO system. The rise of system functionality and the growth of interfaces with high bandwidth in MCUs has resulted in a situation where a CPU-only processing of the IO, or a degraded usage of DMACs, is no more feasible. Therefore, dedicated hardware components, like DMAC, have to be considered and the disadvantages of conflict-affl icted transfers must become part of the analysis. To resolve the problems with interference afflicted MCU internal data transfers, an approach is presented which describes the infl uence parameters on the WCET and expresses these in a simplified timing model of the MCU. Afterwards the information is used to extrapolate the increase of the execution time caused by a given type of traffic to estimate the WCET with asynchronous IO accesses.