| dc.contributor.author | Einer, Stefan | |
| dc.contributor.author | Fechner, Bernhard | |
| dc.contributor.author | Keller, Jörg | |
| dc.date.accessioned | 2017-12-06T08:58:48Z | |
| dc.date.available | 2017-12-06T08:58:48Z | |
| dc.date.issued | 2010 | |
| dc.identifier.issn | 0724-5319 | |
| dc.identifier.uri | http://dl.gi.de/handle/20.500.12116/8523 | |
| dc.description.abstract | Stefan Einer, Schweizerische Bundesbahnen, 3000 Bern, Switzerland, [email protected] Bernhard Fechner, FernUniversität in Hagen, 58084 Hagen, Germany, [email protected] Jörg Keller, FernUniversität in Hagen, 58084 Hagen, Germany, [email protected] | en |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e.V. | |
| dc.relation.ispartof | FERS-Mitteilungen: Vol. 28, No. 1 | |
| dc.relation.ispartofseries | FERS-Mitteilungen | |
| dc.subject | Schedule Algorithm | |
| dc.subject | Data Cache | |
| dc.subject | Instruction Schedule | |
| dc.subject | Conditional Branch | |
| dc.subject | Processor Performance | |
| dc.title | Petri Net Analysis of Non-Redundant and Redundant Execution Schemes | en |
| dc.type | Text/Journal Article | |
| mci.reference.pages | 61-64 | |
| dc.identifier.doi | 10.1007/BF03345446 | |
