A Fault-Tolerant Processor Architecture
| dc.contributor.author | Bouajila, Abdelmajid | |
| dc.contributor.author | Sommer, Thomas | |
| dc.contributor.author | Zeppenfeld, Johannes | |
| dc.contributor.author | Stechele, Walter | |
| dc.contributor.author | Herkersdorf, Andreas | |
| dc.date.accessioned | 2017-12-06T08:58:48Z | |
| dc.date.available | 2017-12-06T08:58:48Z | |
| dc.date.issued | 2010 | |
| dc.identifier.issn | 0724-5319 | |
| dc.identifier.uri | http://dl.gi.de/handle/20.500.12116/8528 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e.V. | |
| dc.relation.ispartof | FERS-Mitteilungen: Vol. 28, No. 1 | |
| dc.relation.ispartofseries | FERS-Mitteilungen | |
| dc.subject | Register File | |
| dc.subject | Fault Injection | |
| dc.subject | Soft Error | |
| dc.subject | RISC Processor | |
| dc.subject | Superscalar Processor | |
| dc.title | A Fault-Tolerant Processor Architecture | en |
| dc.type | Text/Journal Article | |
| mci.reference.pages | 14-19 | |
| dc.identifier.doi | 10.1007/BF03345438 |
