Auflistung nach Autor "Stechele, Walter"
Anzeige der Dokumente 1-11 von 11
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Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays
Sousa, Éricles Rodrigues; Tanase, Alexandru; Lari, Vahid; Hannig, Frank; Teich, Jürgen; Paul, Johny; Stechele, Walter; Kröhnert, Manfred; Asfour, Tamin
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Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays
Sousa, Éricles; Tanase, Alexandru; Lari, Vahid; Hannig, Frank; Teich, Jürgen; Paul, Johny; Stechele, Walter; Kröhnert, Manfred; Asfour, Tamin
80-89 -
An architecture for runtime evaluation of soc reliability
Bernauer, Andreas; Bringmann, Oliver; Rosenstiel, Wolfgang; Bouajila, Abdelmajid; Stechele, Walter; Herkersdorf, Andreas
177-184 -
Combitgen: A new approach for creating partial bitstreams in virtex-II pro devices
Claus, Christopher; Müller, Florian Helmut; Stechele, Walter
122-131 -
A Fault-Tolerant Processor Architecture
Bouajila, Abdelmajid; Sommer, Thomas; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas
14-19 -
Optimization potential of CMOS power by wire spacing
Zuber, Paul; Müller, Florian Helmut; Stechele, Walter
344-348 -
Partial reconfiguration on FPGAs in practice – tools and applications
Koch, Dirk; Torresen, Jim; Beckhoff, Christian; Ziener, Daniel; Dennl, Christopher; Breuer, Volker; Teich, Jürgen; Feilen, Michael; Stechele, Walter
297-319 -
Potentials and challenges for multi-core processors in robotic applications
Herkersdorf, Andreas; Paul, Johny; Kumar Pujari, Ravi; Stechele, Walter; Wallentowitz, Stefan; Wild, Thomas; Zaib, Aurang
2749-2764 -
Self-reconfigurable control architecture for complex robots
Hartmann, Jan; Stechele, Walter; Maehle, Erik
2742-2748 -
Towards a dynamically reconfigurable system-on-chip platform for video signal processing
Stechele, Walter; Herrmann, Stephan; Herkersdorf, Andreas
225-234 -
Workshop „Adaptive and Organic Systems“
Herkersdorf, Andreas; Stechele, Walter; Müller-Schloer, Christian; Schmeck, Hartmut
731-732